Module 5

Interrupts & Power

Mastering the art of doing nothing. How to sleep efficiently and wake up instantly.

LPM3 GIE RETI P1IV

Low Power Modes (LPM)

The MSP430 is a sleep champion. Configure the 4 bits in the Status Register (SR) to shut down clocks and save battery.

SCG1
0
SCG0
0
OSCOFF
0
CPUOFF
0
memory
CPU
speed
MCLK
hub
SMCLK
schedule
ACLK
Select a mode to see effects...

The Evolution of Attention

refresh

1. Polling

The CPU constantly asks: "Are you ready? Are you ready?"

  • × Wastes CPU cycles
  • × Slow response time
  • ✓ Simple hardware
link

2. Daisy Chain

Hardware passes the signal down the line. First come, first served.

  • ✓ Better efficiency
  • ~ Medium complexity
  • ℹ Priority based on position
MSP430
call_split

3. Vectored

Direct jump to the handler function. Fastest response.

  • ✓ Instant response (6 cycles)
  • ✓ No software overhead
  • ✓ Priorities fixed by Index

The Interrupt Lifecycle

1

The Event & The Flag

A peripheral (Timer, GPIO) sets its flag IFG = 1. The CPU checks if IE = 1 and global GIE = 1.

2

Context Save (Hardware Magic)

The CPU automatically does this (taking ~6 cycles):

  • Check current instruction matches interrupt (finishes instr).
  • PUSH PC (Save return address).
  • PUSH SR (Save status/mode).
  • Clear SR (Disable GIE, Wake up CPU).
3

Vector Fetch & ISR

The CPU reads the address from the Vector Table (0xFF80 - 0xFFFF) and jumps to your ISR code.

4

RETI (Return from Interrupt)

Special instruction. It POPs SR and PC back from the stack. The CPU returns to exactly where it was (and importantly, returns to sleep if it was sleeping!).

Complete Example: Toggle LED on Button Press
Setup (in main)
BIS.B #BIT0, &P1DIR    ; P1.0 = output (LED)
BIC.B #BIT1, &P1DIR    ; P1.1 = input (BTN)
BIS.B #BIT1, &P1REN    ; Enable pull resistor
BIS.B #BIT1, &P1OUT    ; Pull-up
BIC.B #BIT1, &P1IFG    ; Clear flag first!
BIS.B #BIT1, &P1IE     ; Enable interrupt
BIS.W #GIE+LPM3, SR   ; Sleep + enable GIE
ISR (Port 1 handler)
P1_ISR:
XOR.B #BIT0, &P1OUT    ; Toggle LED
BIC.B #BIT1, &P1IFG    ; Clear flag
RETI                    ; Return & sleep

; --- Vector Table ---
.intvec PORT1_VECTOR, P1_ISR

Handling Multiple Sources (P1IV)

Simulating Port 1 Interrupts. Click pins to set flags.
Hardware Priority: P1.0 (Highest) > P1.7.

Port 1 Inputs (Click to trigger)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

Hardware Logic (P1IV)

ReadOnly Register
&P1IV = 0x00

*Automatically clears its flag when read!

ISR Code
Waiting...
vs Polling: Without P1IV, you'd have to write `BIT.B #BIT0, &P1IFG` eight times!

The Golden Rules of ISRs

speed

Keep it Short

Do the minimum (set a flag, copy a byte) and exit. Leave heavy processing for `main()`.

block

No Blocking Code

NEVER use `__delay_cycles()` or polling loops inside an ISR. You will freeze the system.

flag

Clear Flags First

Clear an interrupt flag (e.g., `P1IFG`) BEFORE enabling the interrupt to avoid instant unplanned jumps.

layers

Volatile Variables

Variables shared between `main()` and ISRs must be declared `volatile` so the compiler doesn't optimize them away.