Module 2: The CPU - MSP430 Course

The Programmer's Model

CPU Core Registers

Special Function

R0 (PC) Instruction Ptr

R1 (SP) Stack Top

R2 (SR) Status

15-9

V

7-4

GIE

N

Z

C

R3 (CG2) Constant Gen

General Purpose

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

16 Registers. That's it.

In MSP430, we don't have separate registers for data, addresses, or indexes.
R0-R3 are special.
R4-R15 are identical general-purpose workers.

bolt Constant Generator

Why waste a cycle fetching the number "1" from memory? R2 and R3 can pretend to be these numbers instantly:

0

1

2

4

8

-1

The Memory Map (64KB)

0xFFFF

Interrupt Vectors

CODE (FRAM) Direction: Up ->

Unused

RAM (Data) <- Stack grows down

Peripherals (SFRs)
0x0000 - 0x0FFF

0x0000

Unified Memory

Code, Data, and Hardware Registers all live in the same address space. If you write to 0x1C00, you store data in RAM. If you write to 0x0202, you might turn on an LED!

Little Endian Warning ⚠️

Lower byte stored at lower address.

Word: 0xABCD

arrow_right_alt

addr

CD

addr+1

AB

The Addressing Modes Lab

How do we get data from A to B? Explore the 7 modes.

OpCode

Source

Destination

Input Source (As) 2 Bits

00 Register

01 Indexed Family

10 Indirect

11 Indirect+ Family

Dest (Ad) 1 Bit

0: Rn

1: X(Rn)

Instruction Register (IR)

MOV R4, R5

Move content of R4 to R5

Registers

16-Bit MDB --

Address Logic Idle

Memory (RAM)

Cycle Counter

0

Cycles

Waiting...

The Core: 27 Native Instructions

The MSP430 is simple. It only has 27 native instructions to learn.

Movement & Math

MOV // Move
ADD 🚩 // Add
ADDC 🚩 // Add w/ Carry
SUB 🚩 // Subtract
SUBC 🚩 // Sub w/ Carry
CMP 🚩 // Compare

Logic & Bits

AND 🚩 // Logical AND
XOR 🚩 // Logical XOR
BIS // Bit Set (OR)
BIC // Bit Clear
BIT 🚩 // Bit Test
RRA 🚩 // Rotate Right Arith

Flow Control

CALL // Call Subroutine
RETI // Return from Int

Jumps (Conditional)

JEQ/JZ // == 0
JNE/JNZ // != 0
JC/JNC // Carry?
JN // Negative?
JMP // Always

Emulated Instructions

Magic Tricks: Emulated Instructions

The assembler supports 24 "fake" instructions to simplify coding. It translates them into native ones using Constant Generators (R2/R3) or clever register combinations.

Common Operations

CLR dst → MOV #0, dst

INC dst → ADD #1, dst

DEC dst → SUB #1, dst

INCD dst → ADD #2, dst

DECD dst → SUB #2, dst

INV dst → XOR #-1, dst

TST dst → CMP #0, dst

ADC dst → ADDC #0, dst

Bits & Flow

RLA dst → ADD dst, dst

RLC dst → ADDC dst, dst

SBC dst → SUBC #0, dst

NOP → MOV #0, R3

POP dst → MOV @SP+, dst

RET → MOV @SP+, PC

BR dst → MOV dst, PC

CLRC → BIC #1, SR

*Shown: 16 most common. Others include DINT, EINT, SETC, CLRN, etc.

Is MSP430 really RISC?

"It's complicated. It's a modern hybrid."

check_circle RISC Traits

• Small Instruction Set: Only 27 native instructions. Easy to decode.
• Large Register File: 16 general purpose registers (R0-R15). Orthogonal usage.
• Fixed Width: Most instructions are 16-bit aligned.

cancel CISC Traits (The Hybrid Part)

• No Load-Store Architecture: You can do ADD @R5, 4(R6). Direct memory-to-memory math!
• Variable Cycles: Instructions take 1 to 6 cycles depending on addressing modes. (True RISC defines 1 cycle per instruction).

Conclusion: It's a "RISC-like" architecture optimized for code density and low power, not raw throughput.

Talking to the Chip (Core Instructions)

The MSP430 uses 16-bit instructions. There are only three main ways to format them.

Format I Dual Operand Interactive

15-12

MOV

11-8

0101

7

0

6

0

5-4

00

3-0

0110

MOV R5, R6

Format II Single Operand Interactive

15-7

PUSH

3-0